Integrated FPGA Design Flow
Design Creation - º¹ÀâÇÑ HDLµðÀÚÀÎ »ý¼º, °ü¸® ¹× ºÐ¼® Simulation - Ç÷§ÆûÀ̳ª ¾ð¾î¿Í °ü·Ã ¾øÀÌ º¹ÀâÇÑ µðÀÚÀÎ ½Ã¹Ä·¹ÀÌ¼Ç Synthesis - º¹ÀâÇÑ FPGA ±×¸®°í ASIC µðÀÚÀÎÀ» À§ÇÑ Ã·´Ü synthesis