IC Design과 Manufacturing간의 효과적인 handoff
Physical Verification과 DFT사이의 필수적인 연결고리를 제공
AMS SoC 디자인을 위한 단 한 개의 능률적인 디자인 Flow.

Custom Design & Simulation	Design Architect IC ADiT Eldo Eldo RF
Digital Design & Simulation
Mixed Signal Circuit Simulation	ADVance MS ADVance MS RF
Block-Level Physical Design & Verification	Olympus-SoC Pinnacle Calibre nmDRC Calibre LVS Calibre xRC Calibre xL Calibre LFD: Litho-Friendly Design Calibre YieldAnalyzer Calibre YieldEnhancer IC Station SDL Calibre RVE Calibre Interactive
Chip-Level Floorplan & Place & Route	Olympus-SoC Pinnacle Calibre DESIGNrev IC Station SDL
Layout Verification	Olympus-SoC Pinnacle Calibre nmDRC Calibre LVS Calibre YieldAnalyzer Calibre YieldEnhancer Calibre RVE Calibre Interactive
Full-Chip Parasitic Extraction	Calibre xRC Calibre xL Calibre RVE Calibre Interactive
Mask Synthesis	Calibre nmOPC Calibre OPCverify Calibre LFD: Litho-Friendly Design Calibre RET (OPC and PSM) Calibre MDP Calibre nmDRC
Chip Manufacturing & Test	TestKompress FastScan MBISTArchitect YieldAssist